A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme

Abstract

This paper presents a 24 Gbps SerDes transceiver circuit for on-chip high speed serial links for on-chip networks. The transceiver uses a proposed almost-differential self-timed 3-level signaling scheme, which works using a frequency of half the data rate for relaxing the design. Also, the third voltage level is created without the need for an external Vdd/2 supply source. Moreover, a 3-level inverter is proposed for the use in the front-end of both the TX and the RX. The transceiver is designed for a 5mm long lossy on-chip differential interconnect in GF 65nm CMOS technology. It serializes the parallel 3 Gbps 8-bit, and multiplexes them with the 12 GHz input clock. A simple RX extracts both the data and the clock from the same signals.