Should our power approach be current?

Abstract

In the past, power consumption was of little concern to the IC designer. Time-to-market drove the design deadlines, and power consumption was a secondary, if not tertiary, concern. If there were power issues, they could typically be accounted for by tweaking the fabrication process, redesigning after the initial design ship, or even just waiting for the next process change from the fab.Today power has become one of the sign-off qualifiers prior to fabrication, and the metric for success has changed from performance and area to power consumption in nanometer SoC designs, especially in the huge market for handheld/wireless consumer electronics. Although "power" is often the stated concern, current is the real issue. This fundamental paradigm shift requires changes to both the design flow and the tools used for electrical sign-off.