A Comparative Analysis of 8-bit Novel Adder Architecture Design using Traditional CMOS and m-GDI technique

Abstract

Addition is a standout amongst the most fundamental operations in VLSI frameworks such as microprocessors and digital signal processing systems. Therefore, the adders must render a high speed operation into existence. This paper proposes a novel implementation of 8-bit adder architecture using modified Gate Diffusion Input (m-GDI) approach. The primary blocks of adder are partial full adder, 1-bit full adder, 4-bit ripple carry adder (RCA), 4-bit carry look ahead adder (CLA). The proposed adder architecture devours 70% lesser area, 71 % lesser delay and 35% lesser power dissipation w.r.t traditional CMOS design. The proposed adder is implemented utilizing Cadence Virtuoso Tool in 180nm technology.