LAKE: a performance-driven analog CMOS cell layout generator

Abstract

LAKE is an automatic layout generator that lays out CMOS analog integrated circuits subject to circuit layout constraints such as: matching, symmetry, signal coupling cell aspect ratio (or cell height), and specified cell input/output pin locations. Unlike most previous works, LAKE focuses on effective rules and methods that suit any type of CMOS analog circuit to be incorporated in an application-specific mixed analog digital layout system. Placement is based on the characteristics of circuit structure and the layout constraints. The proposed slot structure provides the capability of handling fully symmetric layouts. The simulated evolution process evaluates the quality of layout based detailed layout information in pursuing minimal parasitic effects on circuit performance. We test some real life examples. The design experiments have shown that LAKE can produce manual-quality analog layouts.