Power Distribution Network optimization for Associative Memories

Abstract

Associative memories are massively parallel circuits which perform a parallel comparison between stored data and input data. When operated in parallel comparison mode, they require high current spikes (in the order of few amperes) at every clock edge, and the voltage drop due to current spikes can seriously affect the circuit operation. This paper proposes a method to enhance the power integrity, both at package level and at chip level. This work aims at avoiding “bounce” effects on supply voltages, and at keeping the supply voltage ripple below one hundred millivolts during the comparison mode. A technique to mitigate the voltage ripple consists in placing decoupling capacitors on the Power Delivery Network (PDN). This technique can be applied both at the chip level and at the package level. We show that this technique allows us to keep the power network impedance below 0.1 Ω within the relevant bandwidth of the circuit.