Efficient Sequence Generation for Hardware Verification Using Machine Learning

Abstract

With the doubling in the number of transistors approximately every two years, modern systems' complexity is growing exponentially. As the complexity of systems increases, the amounts of data generated during functional verification becomes huge. Debugging this huge amount of data becomes very time-consuming and a bottleneck in the design flow. Thus, comes the importance of using machine learning in verification to analyze this huge amount of data, automate and accelerate the process of verification. In this paper, two methods for improving sequential circuits' simulation-based verification techniques are presented. First, a graph-based method with adaptive neural network is proposed. The proposed method overcomes the problem of sensitivity of learning algorithms to the size and quality of the initial training set. Simulations show that the proposed method always achieves full coverage closure irrespective of the initial training set while the other methods quality decreases drastically with decreasing training set size. For the second method, a new way of choosing graph weights is proposed. Results show that new graph weights introduce at least 10% improvement in total number of instructions and 40% improvement in total time.