Trans_Proc: A Reconfigurable Processor to Implement The Linear Transformations

A. Sanyal, A. Sinha
{"title":"Trans_Proc: A Reconfigurable Processor to Implement The Linear Transformations","authors":"A. Sanyal, A. Sinha","doi":"10.4018/ijsi.303575","DOIUrl":null,"url":null,"abstract":"A reconfigurable transform processor is proposed and implemented here. Firstly, a brief study of processors implementing different transformations is presented. We have categorized the transform processor as the one which can implement a number of linear transforms using reconfigurability. The theoretical suitability regarding the architecture of the processor is proved by graph theory method. Then the complete architecture of the overall processor and the processing element is presented and implemented using VHDL. The complete instruction set suitable to the processor is designed. The instructions are mapped to the sequence of control signals. Generating sequence of control signals for every type of instructions would finally create a hardwired control unit for the processor which was also presented. Next the processor is fed with data to simulate it. A three-phase simulation is carried out to prove the correctness of the design. Finally the same processor with a data bus width of 32 to 512 is implemented and compared in terms of speed and size.","PeriodicalId":396598,"journal":{"name":"Int. J. Softw. Innov.","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Int. J. Softw. Innov.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4018/ijsi.303575","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

A reconfigurable transform processor is proposed and implemented here. Firstly, a brief study of processors implementing different transformations is presented. We have categorized the transform processor as the one which can implement a number of linear transforms using reconfigurability. The theoretical suitability regarding the architecture of the processor is proved by graph theory method. Then the complete architecture of the overall processor and the processing element is presented and implemented using VHDL. The complete instruction set suitable to the processor is designed. The instructions are mapped to the sequence of control signals. Generating sequence of control signals for every type of instructions would finally create a hardwired control unit for the processor which was also presented. Next the processor is fed with data to simulate it. A three-phase simulation is carried out to prove the correctness of the design. Finally the same processor with a data bus width of 32 to 512 is implemented and compared in terms of speed and size.
Trans_Proc:实现线性转换的可重构处理器
本文提出并实现了一种可重构的变换处理器。首先,简要研究了实现不同转换的处理器。我们将转换处理器分类为可以使用可重构性实现许多线性转换的处理器。用图论方法证明了该处理器结构的理论适用性。然后给出了整个处理器和处理单元的完整体系结构,并用VHDL语言进行了实现。设计了适合该处理器的完整指令集。指令被映射到控制信号序列。为每种类型的指令生成控制信号序列,最终为处理器创建一个硬连线控制单元。接下来,处理器被输入数据来模拟它。通过三相仿真验证了设计的正确性。最后实现了数据总线宽度为32 ~ 512的同一处理器,并在速度和大小方面进行了比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信