Sehyuk Ann, Junho Yu, Jusang Park, Yongsik Kim, Namsoo Kim
{"title":"Low Power CMOS 8:1 Injection-Locked Frequency Divider with LC Cross-Coupled Oscillator","authors":"Sehyuk Ann, Junho Yu, Jusang Park, Yongsik Kim, Namsoo Kim","doi":"10.1109/EMS.2015.70","DOIUrl":null,"url":null,"abstract":"This paper proposes a high performance frequency divider which is composed of injection-locked frequency divider (ILFD) and current-mode logic (CML) frequency divider. The multiple-block divider is to obtain the broad-band and high frequency operation in phase-locked loop (PLL). ILFD has a similar structure with LC cross-coupled oscillator which operates at 20 GHz. 3 stages of ILFD are supposed to provide the operation of divide-by-8 (/8) with low power consumption and are to adjust the frequency alignment with the LC cross-coupled oscillator. CML frequency divider which is used as the 2nd block of divider applies an inductive peaking structure in order to increase the bandwidth. The proposed frequency divider which has the /8 ILFD and /32 CML frequency divider is integrated with 0.18 μm CMOS process and operates in the conventional PLL. Simulation test shows the low power consumption of 13.2 mW at the input frequency of 20 GHz.","PeriodicalId":253479,"journal":{"name":"2015 IEEE European Modelling Symposium (EMS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE European Modelling Symposium (EMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMS.2015.70","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper proposes a high performance frequency divider which is composed of injection-locked frequency divider (ILFD) and current-mode logic (CML) frequency divider. The multiple-block divider is to obtain the broad-band and high frequency operation in phase-locked loop (PLL). ILFD has a similar structure with LC cross-coupled oscillator which operates at 20 GHz. 3 stages of ILFD are supposed to provide the operation of divide-by-8 (/8) with low power consumption and are to adjust the frequency alignment with the LC cross-coupled oscillator. CML frequency divider which is used as the 2nd block of divider applies an inductive peaking structure in order to increase the bandwidth. The proposed frequency divider which has the /8 ILFD and /32 CML frequency divider is integrated with 0.18 μm CMOS process and operates in the conventional PLL. Simulation test shows the low power consumption of 13.2 mW at the input frequency of 20 GHz.