Sub-1V capacitor-free low-power-consumption LDO with digital controlled loop

Abstract

A CMOS sub-1 V capacitor-free low-power-consumption low-dropout voltage regulator (LDO) with digital controlled loop is presented in this paper. This technique can make power consumption lower than other LDOs with traditional controlled Loop. Especially, the performance of power consumption of proposed LDO without off-chip capacitors is excellent. The LDO can also be stable even without the output capacitor. With 0.9 V power supply voltage, the output voltage is designed as 0.6 V. The maximum output current of the LDO is 120 mA at an output of 0.6 V. The prototype of the LDO is fabricated with TSMC 0.35-mum CMOS processes. The chip area (including I/O pad) is only 927 mum times 969 mum.