Design of a ternary RS-trigger

Abstract

The paper considers the design of ternary elements and the development of computer systems on their basis. Instead of the common binary logic, a ternary computer uses the logic with three possible values in the calculations. Currently, there are no common decisions on the design of the ternary elements. The paper proposes a design of a ternary RS-flip-flop trigger, which is built on the basis of a multi-threshold element of the multi-valued logic. A designed ternary RS-trigger has one input line with three different levels of input signals and three levels of output signals (-1, 0, +1), giving nine different combinations. A proposed RS-trigger does not have any forbidden states or levels of an input signal. A proposed ternary trigger can serve as a base for the future design of the memory, registers, digital automats etc. in ternary computing systems.