Design of a rail-to-rail 460 kS/s 10-bit SAR ADC for capacitive sensor interface

Abstract

A 460 kS/s 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with rail-to-rail input range is proposed for acquiring capacitive sensor. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor (SC) capacitance-to-voltage converter (C2V). A bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability. The charge redistribution converter is realized by a single-ended cascaded binary-weighted (CBW) capacitive digital-to-analog converter (DAC). Self-timing SAR logic borrows extra half cycle relaxing the settling of preamps and reduces the power consumption. At a sample rate of 460 kS/s, the 10-bit SAR ADC achieves an ENOB of 9.9 bit and consumes 35 μW with 1.8 V power supply, resulting in an energy efficiency of 80 fJ/step. The circuits are designed and simulated with parasitic models using a commercially available 180 nm CMOS process.