A Motion Estimation Search Algorithm and its Hardware Implementation for HEVC/H.265

Abstract

In this paper, a new alternating Motion Estimation (ME) search pattern algorithm and its hardware architecture have been proposed. The number of search points in the algorithm is reduced to (24 and 26) compared to Test Zonal Search(TZS)(77 for diamond search pattern and 81 for square search pattern). The proposed algorithm takes 7.89% and 8.47% less encoding time with a small increase in Bjøntegaard delta bitrate (BD-BR) 1.18% and 2.38% compared to the TZS algorithm. The proposed architecture was implemented in the FPGA platform and operates at 162 MHz. It can process 8K UHD (8192×4320)@78 fps.