Low-Power Architectures for Spike Sorting

Abstract

Front-end integrated circuits for spike sorting will be useful in neuronal recording systems that engage a large number of electrodes. Detecting, sorting and encoding spike data at the front-end will reduce the data bandwidth and enable wireless communication. Without such data reduction, large data volumes need to be transferred to a host computer and typically heavy cables are required which constrain the patient or test animal. Front-end processing circuits must dissipate only a limited amount of power, due to supply constraints and heat restrictions. Two reduced complexity spike sorting algorithms are introduced, one based on integral transform and another on segmented PCA. The former achieves 98% of the precision of a PCA sorter, while requiring only 2.5% of the computational complexity. The latter algorithm is somewhat more accurate but incurs a higher complexity