Energy Efficient and High Performance Modified Mesh based 2-D NoC Architecture

Abstract

System-on-chip (SoC) has migrated from single core to multi core architectures to adapt the expanding intricacy of real time applications. Network-on-chip (NoC) is appeared as an alternative to deal with the communication issues in embedded system-on-chip architectures. In network-on-chip (NoC) design, application mapping plays a significant role. In this research paper, a modified 2-D mesh NoC architecture is introduced and proposed an effective mapping algorithm, which maps the cores in the modified NoC architecture based on a core efficient region (CER) to enhance the processor performance and reduces the communication energy. The outcomes of the simulation illustrate that the proposed strategy is outperformed comparing with the other mapping techniques in terms of communication energy and performance. Moreover, the proposed algorithm is relevant to both random and distributed core graphs.