{"title":"CKKS-Based Homomorphic Encryption Architecture using Parallel NTT Multiplier","authors":"T. Tan, Jisu Kim, Hanho Lee","doi":"10.1109/ISCAS46773.2023.10181714","DOIUrl":null,"url":null,"abstract":"This paper presents a high-throughput CKKS-based encryption architecture for homomorphic encryption. By de-ploying a parallel number theoretic transform (NTT) multiplier architecture, the polynomial multiplication is significantly accel-erated. Additionally, the modular multiplier is also improved by efficiently implementing using digital signal processing resources. The proposed NTT multiplier and homomorphic encryption architecture are evaluated using Xilinx Vivado and Xilinx XCU250 FPGA board. The evaluation results demonstrate that the proposed NTT multiplier helps improve the throughput of polynomial multiplication by at least 1.5 x compared to the most recent works. The efficiency of the proposal NTT multiplier, calculated by throughput per L UT or Slice, is much better than that of existing studies. The proposed homomorphic encryption architecture using the proposed NTT multiplier offers a high throughput of 32.7 Gbps.","PeriodicalId":177320,"journal":{"name":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS46773.2023.10181714","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a high-throughput CKKS-based encryption architecture for homomorphic encryption. By de-ploying a parallel number theoretic transform (NTT) multiplier architecture, the polynomial multiplication is significantly accel-erated. Additionally, the modular multiplier is also improved by efficiently implementing using digital signal processing resources. The proposed NTT multiplier and homomorphic encryption architecture are evaluated using Xilinx Vivado and Xilinx XCU250 FPGA board. The evaluation results demonstrate that the proposed NTT multiplier helps improve the throughput of polynomial multiplication by at least 1.5 x compared to the most recent works. The efficiency of the proposal NTT multiplier, calculated by throughput per L UT or Slice, is much better than that of existing studies. The proposed homomorphic encryption architecture using the proposed NTT multiplier offers a high throughput of 32.7 Gbps.