Area-delay-power-aware adder placement method for RNS reverse converter design

Abstract

Residue number systems (RNS) are an attractive alternative to conventional weighted number systems for nowadays applications, due to features such as parallelism and low-power consumption. However, a prerequisite for benefiting from these features is to have a suitable design for reverse converters. This paper proposes a practical adder placement method to achieve reverse converters with the desired characteristics based on the target application's requirements and constraints. The presented area-delay-power-aware adder placement method breaks down into four phases. Besides, a linear efficiency function specified for RNS is introduced to choose design with the best trade-off between circuit parameters. The effectiveness of the proposed placement method is experimentally assessed.