Tolerating hard faults in microprocessor array structures

Fred A. Bower, Paul G. Shealy, S. Ozev, Daniel J. Sorin
{"title":"Tolerating hard faults in microprocessor array structures","authors":"Fred A. Bower, Paul G. Shealy, S. Ozev, Daniel J. Sorin","doi":"10.1109/DSN.2004.1311876","DOIUrl":null,"url":null,"abstract":"In this paper, we present a hardware technique, called self-repairing array structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch history table. SRAS masks errors that could otherwise lead to slow system recoveries. To detect row errors, every write to a row is mirrored to a dedicated \"check row\". We then read out both the written row and check row and compare their results. To correct errors, SRAS maps out faulty array rows with a level of indirection.","PeriodicalId":436323,"journal":{"name":"International Conference on Dependable Systems and Networks, 2004","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"104","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Dependable Systems and Networks, 2004","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSN.2004.1311876","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 104

Abstract

In this paper, we present a hardware technique, called self-repairing array structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch history table. SRAS masks errors that could otherwise lead to slow system recoveries. To detect row errors, every write to a row is mirrored to a dedicated "check row". We then read out both the written row and check row and compare their results. To correct errors, SRAS maps out faulty array rows with a level of indirection.
微处理器阵列结构的硬故障容忍度
在本文中,我们提出了一种硬件技术,称为自修复阵列结构(SRAS),用于掩盖微处理器阵列结构中的硬故障,如重排序缓冲区和分支历史表。SRAS屏蔽了可能导致系统恢复缓慢的错误。为了检测行错误,对一行的每次写入都会镜像到专用的“检查行”。然后我们读出写行和校验行,并比较它们的结果。为了纠正错误,SRAS用一定程度的间接映射出有错误的数组行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信