Efficient Reconfiguration Algorithm for Three-dimensional VLSI Arrays

Abstract

Reconfigurable VLSI array is a well known fault tolerant architecture for parallel computing, but few reconfiguration approaches are reported so far for three-dimensional (3D) arrays due to the high complexity of reconfiguration. This paper is devoted to develop reconfiguration algorithm for three-dimensional degradable VLSI arrays. Three bypass schemes and three rerouting schemes are proposed to reconfigure a 3D host array with faults resulting in a target sub-array without faults. Moreover, a heuristic algorithm based on plane rerouting is proposed to construct a target sub-array on the selected rows and columns. It is also proved that the reconfiguration problem considered in this paper on the selected rows and columns(MPSRC) can be optimally solvable in linear time. Empirical study shows that the proposed algorithm produces target arrays with good harvest for the case of the fault rate no more than 5%, that is often occurred in real applications.