The optimum Booth radix for low power integer multipliers

Abstract

This paper investigates the optimum Booth integer multiplier for low power applications. Booth radix-4, radix-8 and radix-16 were compared for area, speed and power using standard-cell ASIC design flow and 28nm CMOS technology. All of the investigated designs were implemented in RTL, fully verified and then synthesized using 28nm standard-cell libraries which have low leakage slow cells, regular leakage average-speed cells and high-leakage fast-speed cells. The area, speed and power were compared to determine the best choice for low power designs. Among the three investigated designs, the Booth radix-4 was the best choice, it had the lowest area, power and fastest execution speed among the 3-choices. It is worthy of note that radix-8 had lower leakage power and overall power among the three designs when implemented using LVT cells. So for power sensitive and high-speed applications radix-8 could be a better choice with overhead of about 18% area and 3% slower.