A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells

Abstract

Register file is often implemented using static random access memory (SRAM) due to its fast operation. Furthermore, SRAM-based multi-port register file can perform multiple read and write operations simultaneously, thus increasing data throughput in embedded systems and meeting the expected demands of parallel or pipelined microprocessors. With the continuous scaling of transistor feature size, designing low power robust register file for microprocessors and investigating their failure characteristics become critical. In this work, the authors present a register file with a structure of 3-port SRAM cell and a differential current-mode sense amplifier for read circuitry. The authors then study the fault models for resistive defect within the SRAM cell and its failure boundary. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Experimental results show that the proposed current-mode sensing scheme has improvements for memory fault-tolerance of resistive defect at 4-6times for dual-port read and 5.8times for 3-port read compared to voltage-mode sensing with 0.18mum manufacturing process technology