An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations

Abstract

This paper proposes an area-efficient single-phase-clocked and contention-free flip-flop (FF) targeting ultra-low-voltage (ULV) operations, named TSPC20. To ensure reliable operations in ULV regime, we eliminate all the contention paths and cut off the longest hold time path consisting of three stacking transistors in the conventional single-phase-clocked FF (TSPC18). Moreover, to further reduce the area and power consumption, we remove the redundant transistors through transistor merging and logical expression reorganization. TSPC20, with only 20 transistors, is the most area-efficient FF compared to prior FFs that can operate in ULV regime. Post-layout simulations with 28nm process shows that TSPC20 achieves 48% (54%) power reduction at 0.3V/6Mhz (0.9V/1.4GHz) considering 10% data activity ratio, compared to the conventional transmission-gate flip-flop (TGFF). The 1K Monte Carlo simulations verify that TSPC20 is functional down to 0.3V.