Migrating an OS Scheduler into Tightly Coupled FPGA Logic to Increase Attacker Workload

Abstract

This paper explores the idea of increasing attacker workload by hiding core operating system functions within Field Programmable Gate Array (FPGA) logic, recently introduced within the fabric of high-performance embedded processors. The research is conducted in the context of a from-scratch micro-kernel operating system (BEAR [1]) under development at Dartmouth. This paper explains the performance costs and security enhancements associated with a rudimentary hardware scheduler on the Xilinx Zynq Z-7020 All Programmable System-on-Chip. Baseline measurements are collected for a traditional C-based software implementation. Implementations coded directly in VHDL and transformed from C to HDL via High Level Synthesis (HLS) are then compared. Performance and hardware resource utilization costs between AXI4 and AXI4-lite processor-FPGA interfaces are also evaluated.