Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash

Abstract

Ferroelectric-metal field-effect transistor (FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for multi-level cell (MLC) operation. The FeMFET with a gate-stack of metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) is used for improving memory window to $1.60\mathrm{~V}$ and alleviating variability caused by ferroelectric phase variation for MLC operation. In addition, the read-out current is examined by increasing the vertical gate-stack from 256-layer to 512-layer using page buffer circuit for sensing operation. Leveraging TCAD modeling and SPICE simulation, we demonstrate that FeMFET-based 3D NAND can operate 512-layer with sufficient sense margin for MLC operation.