Very low voltage CMOS two-stage amplifier

Abstract

A minimum-supply rail-to-rail differential stage architecture is presented. It exhibits easy cascading features and unlike previous similar solutions does not critically affect CMRR. Starting from this block, a fully-differential two-stage amplifier is designed using 0.7-V supply in a 130-nm CMOS technology. Simulations show a 47-dB dc differential gain with a gain-bandwidth product of 700 MHz, and 70-dB CMRR at dc, under a total nominal current consumption lower than 2 mA.