Performance Optimization of Vertical Gaussian Doped SOI Junctionless FET with Substrate Bias Effects

Abstract

This paper presents a TCAD simulation based study of channel potential, threshold voltage, drain induced barrier lowering and subthreshold swing of vertical Gaussian doped SOI Junctionless FET with back bias effects. The subthreshold characteristics of the proposed structure are optimized using the straggle parameter and substrate bias voltage. It is shown that controlling the doping concentration in the channel and substrate bias improves the channel electrostatics in SOI Junctionless FET, thus, enhances the subthreshold performance.