Fault coverage analysis using fault model and functional testing for DPM reduction

Abstract

In today's fast growing and increasing complex world of VLSI circuits, test quality has significant effect on the quality of the product. A malfunctioning circuit is a result of design flaw, manufacturing defects or both. Testing is used as a measure to estimate the quality of design. High quality testing minimizes defect-per-million (DPM) and thus can significantly reduce manufacturing costs and increase product yield. Automatic test pattern generator (ATPG) is one of the structural methods used to get good coverage. To estimate the overall outgoing DPM(Defective Parts per Million) in High Volume Manufacturing (HVM) functional test cases are written manually in order to target the areas which are not detected by structural testing methods like ATPG (Automatic Test Pattern Generator). When the test vectors are used for manufacturing testing, their quality for detecting manufacturing defects needs to be evaluated. Fault simulation is known to be a reliable means for determining the single stuck-at fault coverage provided by a set of test vectors. The degree to which a test vector suite detects the faults is known as the fault coverage of the suite. This procedure referred as fault grading.