IP Core of Serial Peripheral Interface (SPI) with AMBA APB Interface

Abstract

the model and design of the IP core of APB interfacing with SPI is presented. In this work, the SPI interface can send or receive data from a single slave and efficient APB-SPI controller with flexible data width and frequency. The SPI is simulated by ModelSim, QuartusLite 16 and will be synthesized to produce the gdsii file for tape out. The findings of the SPI interface to send or receive data from a single slave and efficient APB-SPI controller with flexible data width and frequency is proven for maximum frequency of 16 MHz.