Reliability challenges of high performance PD SOI CMOS with ultra-thin gate dielectrics

Abstract

In this paper we have discussed various reliability issues in developing cutting edge SOI technologies with ultra-thin gate dielectrics such as DC-HCI (hot carrier injection), TDDB, NBTI, and ESD. Floating body and body tied structures on partially depleted SOI substrate are investigated. The correlation between the AC and DC HCI degradation are compared and found to have a larger voltage scaling factor that can be explained by self-heating. The reliability of the gate dielectric is evaluated by time dependent dielectric breakdown (TDDB). The results imply that the addition of a T-gate shortens gate dielectric lifetime, this is because part of the gate dielectric is biased in accumulation and thus has shorter lifetime. Negative bias temperature instability (NBTI) lifetime improves with higher nitrogen concentration in the GOX but it is found that it can cause more positive charge generation during NBTI stress. Electrostatic discharge (ESD) is the major reliability issue, ESD failure mechanism is thermal runaway that is due to the increased self-heating. A typical protection of the increased self-heating is the lateral diode. Change in design of the lateral diode to floating gate electrode enhanced the charged device model (CDM) protection capability.