An in-circuit debug environment for multiprocessor SOCs based on a HDL RISC soft-core

Abstract

A fundamental feature common to all SOC projects is the inclusion of one or more embedded microprocessors in the design space. As the complexity of algorithms mapped on embedded processors and their interaction with the surrounding SOC resources increase, the availability of reliable software verification means becomes a serious design issue, especially when more than one processor is included in the design. Many existing processor-debugger interfaces are based on specific technology or architectural features such as JTAG interfaces or scan-chains. On the other hand, embedded microprocessor cores are often HDL suites, quite parametric and technology independent, and need to be reused in a very different design environment. In this paper, an in-circuit software debug environment is presented, that can be utilized for single- or multi-processor SOCs. The described methodology, only based on VHDL blocks and software routines, is independent from the chosen technology support, and processor memory or bus architecture configuration.