A fault-tolerant parallel processor modeled by a linear cellular automaton

Abstract

The authors present the fundamental concepts for realizing a fault-tolerant parallel processor modeled by a linear cellular automaton. They give the reconfiguration scheme under this model. They treat the processing elements in the processor as cells of the cellular automaton. They regard the operating states of the elements as states of the cells. The processor can be reconfigured easily and quickly by changing the states of its processing elements when faults are detected. The reconfiguration scheme for the processor utilizes the characteristics of polynomial rings over GF(q), where q is a power of a prime number.<>