Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs

Meng-Ju Wu, D. Yeung
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引用次数: 62

Abstract

Reuse distance (RD) analysis is a powerful memory analysis tool that can potentially help architects study multicore processor scaling. One key obstacle though is multicore RD analysis requires measuring concurrent reuse distance (CRD) profiles across thread-interleaved memory reference streams. Sensitivity to memory interleaving makes CRD profiles architecture dependent, preventing them from analyzing different processor configurations. For loop-based parallel programs, CRD profiles shift coherently to larger CRD values with core count scaling because interleaving threads are symmetric. Simple techniques can predict such shifting, making the analysis of numerous multicore configurations from a small set of CRD profiles feasible. Given the ubiquity and scalability of loop-level parallelism, such techniques will be extremely valuable for studying future large multicore designs. This paper investigates using RD analysis to efficiently analyze multicore cache performance for loop-based parallel programs, making several contributions. First, we provide in depth analysis on how CRD profiles change with core count scaling. Second, we develop techniques to predict CRD profile scaling, in particular employing reference groups to predict coherent shift, and evaluate prediction accuracy. Third, we show core count scaling only degrades performance for last level caches (LLCs) below 16MB for our benchmarks and problem sizes, increasing to 64 -- 128MB if problem size scales by 64x. Finally, we apply CRD profiles to analyze multicore cache performance. When combined with existing problem scaling prediction, our techniques can predict LLC MPKI to within 11.1% of simulation across 1,728 configurations using only 36 measured CRD profiles.
相干轮廓:为基于环路的并行程序实现多核缩放的有效重用距离分析
重用距离(RD)分析是一种强大的内存分析工具,可以潜在地帮助架构师研究多核处理器的可伸缩性。然而,一个关键的障碍是多核RD分析需要测量跨线程交错内存引用流的并发重用距离(CRD)概况。对内存交错的敏感性使CRD配置文件依赖于体系结构,从而阻止它们分析不同的处理器配置。对于基于循环的并行程序,由于交错线程是对称的,所以随着核数的缩放,CRD配置文件会一致地向更大的CRD值移动。简单的技术可以预测这种变化,使得从一小组CRD剖面分析大量多核配置成为可能。考虑到循环级并行的普遍性和可扩展性,这些技术对于研究未来的大型多核设计将是非常有价值的。本文研究了利用RD分析来有效地分析基于循环的并行程序的多核缓存性能,并做出了一些贡献。首先,我们深入分析了CRD配置文件如何随岩心计数缩放而变化。其次,我们开发了预测CRD剖面缩放的技术,特别是使用参考组来预测相干位移,并评估预测精度。第三,我们显示,对于我们的基准测试和问题大小,内核计数缩放只会降低低于16MB的最后一级缓存(LLCs)的性能,如果问题大小缩放64倍,则会增加到64 - 128MB。最后,我们应用CRD配置文件来分析多核缓存性能。当与现有的问题缩放预测相结合时,我们的技术可以仅使用36个测量的CRD剖面,在1,728个配置中预测LLC MPKI的模拟精度在11.1%以内。
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