Efficient data coding schemes to reduce power consumption in NoC

Abstract

Network-on-Chip (NoC) is basic part of given system. It is substitution for System-on-Chip to decrease the complexity. Large numbers of different data packets are sent at a time through different links, known as parallelism. But instead of degrading the performance, NoC keeps on growing in performance and scalability. In nanometer CMOS technology, interconnection of links dominates both performance and scalability. Comparison of encoding and decoding operations is done with the help of output waveforms. Power analysis chart tells about different parameters. Depending on that more efficient and less power consumed technique, scheme-3 is detected. FPGA and Xilinx are two key points of given system. By using Xilinx software, power consumption report is calculated from X-power analyzer to compare three schemes. Also, it will show more efficient technique amongst three.