Multiple-valued dynamic source-coupled logic

T. Hanyu, A. Mochizuki, M. Kameyama
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引用次数: 6

Abstract

A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evaluate logic style makes steady current flow cut off, thereby greatly saving the power dissipation. A combination of SCL and dynamic logic styles makes it possible to reduce the power dissipation while maintaining a highspeed switching capability due to small input-voltage swing with SCL. As a typical example of a high-performance arithmetic circuit, a radix-2 signed-digit adder based on the proposed dynamic SCL is implemented in a 0.18-/spl mu/m CMOS technology. Its power dissipation is reduced to about 33 percent in comparison with that of the corresponding binary CMOS implementation under the normalized switching delay.
多值动态源耦合逻辑
提出了一种基于动态源耦合逻辑(SCL)的多值电流模式(MVCM)集成电路,用于低功耗VLSI。采用预充评估逻辑方式,使恒流切断,从而大大节省了功耗。SCL和动态逻辑风格的结合使得降低功耗成为可能,同时由于SCL的输入电压摆动小而保持高速开关能力。作为高性能算术电路的一个典型例子,采用0.18-/spl mu/m的CMOS技术实现了基于动态SCL的基数-2符号加法器。在标准化开关延迟下,与相应的二进制CMOS实现相比,其功耗降低到约33%。
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