A 204 GHz Power Amplifier with 6.9dBm Psat and 8.8dB Gain in 65nm CMOS Technology

Abstract

This paper presents the design of a 204GHz power amplifier fabricated in TSMC 65nm CMOS process. The power amplifier employs 4 parallel chains of 8 gain stages with novel input and output series combining transformers. The 4:1 divider transformer at the input is driven in staggered anti-phase, which results in less than 2dB of insertion loss. The active stage layout has been modified to push the maximum oscillation frequency (fmax) by more than 50GHz. The power amplifier produces peak output power of 6.9dBm with 8.8dB of peak power gain at 204GHz, with a PAE of 1%. The active region occupies 0.17mm2 of die area.