Retiming for circuits with enable registers

Abstract

This paper presents a new method for improving the timing behaviour of digital circuits, which contain enable-registers and, e.g., come from the high level synthesis. Known techniques optimize all long combinational paths assuming only one clock cycle between registers. But enable-registers cause also paths having more time than one clock cycle. The consideration of this paths leads to a larger optimization potential. As a second topic in the presented method a register relocation is performed for a circuit containing enable registers and D-Flipflops. A suitable retiming algorithm is developed for such circuits.