Efficient Implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures

Abstract

This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, performance of multipliers implemented in FPGA architectures does not allow to constructs high performance digital filters. In this paper application of distributed arithmetic is demonstrated. Since in this approach combinational LUT blocks replace general purpose multipliers, it is possible to construct digital filters of very high performance. However LUT blocks can be of considerable size thus advanced synthesis methods have to be used to map them efficiently into FPGA resources. In this paper and application of the functional decomposition based synthesis has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures and allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.