A large-scale ATM switch: analysis, simulation, and implementation

Abstract

In this paper, a large-scale ATM switch is presented, and its performance is examined through a mathematical analysis and a computer simulation. The implementation of the proposed ATM switch is also discussed. For the performance evaluation of the ATM switch, cell loss rate, cell switching delay, and throughput are found under varying external conditions, such as input traffic load and buffer size of the switching elements, which are the basic building blocks of the proposed ATM switch. The proposed ATM switch behaves well and yields good performance results under a uniform traffic environment. The complexity of the proposed ATM switch is rather moderate and hardware implementation using current technology is feasible up to a switch dimension of 1024/spl times/1024. The ATM switches of such dimension and performance are suitable for installation in high-speed network infrastructure.