A SCA-resistant processor architecture based on random delay insertion

Abstract

Random delay insertion is a simple and efficient approach to counter side-channel attacks, but previous methods do not have the ideal protective effect. In this article, based on random delay insertion, an effective processor architecture resistant to side-channel attacks was proposed. It used a combination of randomized scheduling, randomized instruction insertion and randomized pipeline-delay to resist side-channel attacks. On the base of ARM7 processor, we implemented this architecture and the implementation results showed that this processor has increased approximate 24.3% in hardware area than the original ARM7 processor. The CPA attack experiment results suggested that our new secure processor have high capacity to resist side-channel attacks and thus could be used in USBKEY, Smart CARD and other application scenarios which require extremely high security level.