Sorting out Integration Snags by Using Actual Automatic Test Equipment for Simulations

Abstract

Using digital testing hardware (actual Test Equipment) and software on a defined hardware and software platform produces a means to simulate high I/O chips and chips with no model information. This is taking digital simulation to the next level. The next level is utilizing actual test equipment (ATE) to perform digital simulations on specific devices during Unit Under Test (UUT) simulations. It is technically efficient for both functional testing and diagnostic testing to represent chip or device behavior, especially undocumented behavior and anomalies on actual ATE during simulation. Hardware modeling is the technique of using a physical device to model its own behavior during simulation. Hardware modeling systems format inputs from the simulator, apply the inputs to the physical device, evaluate device behavior, and then return the resulting outputs, plus timing information, to the simulator. By incorporating the physical device and a flexible, behavioral shell, hardware models combine functional accuracy, including unknown propagation, with complex timing information, including mode-dependent delays and timing checks. Using actual ATE during this simulation process secures chip or device functioning during stimulus and response vector sequences. This paper will discuss techniques associated with performing simulation using actual ATE. Also discussed will be the prolific capabilities of these applications.