FPGA Implementation of Reversible LFSR with Primitive Polynomial using Verilog HDL

Abstract

Linear Feedback Shift Register (LFSRs) based pseudo-random number generators (PRNGs) are used in test pattern generators (TPGs). Because FPGAs are reprogrammable, you can implement designs of LFSR on FPGA and simulate different lengths. It is important to test and validate the simulated results and synthesis results. The primitive polynomial determines the total number of pseudo-random output states of LFSRs. If the polynomial used is a primitive, the output random state is up to 2n- 1 state. This paper presented the designed, developed, and implemented 4, 8, 16, and 32 bit reversible LFSRs in FPGAs by performing, analyzing, and investigating random behavior using the Verilog HDL code. The analysis is performed to find the design speed requirements in FPGA when the number of constant inputs, the number of garbage outputs, the number of reversible logic gates, and the increased number of bits. In this paper, shows a comparative study of 4, 8, 16, and 32 bit reversible LFSRs on FPGAs to understand their performance. According to the results, the proposed reversible LFSR design using the Pareek gate approach reduces power by 10% when compared to the irreversible approach. As a result, the proposed design is used to develop Built-In-Self-Test (BIST) module.