A simplified module interface style for synthesis education

Abstract

In the synthesis course at Stony Brook we have made it possible for students to complete the tasks of specification, simulation, synthesis, FPGA fitting, low level verification, both on homework sets and on a non-trivial project, all within one semester. We do it by using a set of standard components and a consistent and standardized interface throughout: for the library components, for the designs themselves, and for the testbenches. It is possible to get designs working quickly because the control is implicit and the synthesis scripts are standardised, even though the projects covered a range from radix 4 multiplication and division, memory interleaver, a synchrotron controller, and parts for a 3 dimensional graphics engine. The paper summarizes the method and illustrates it on a design for a RAM built-in self-test.