The performance and reliability of NIST 10-V Josephson arrays

Proceedings of Conference on Precision Electromagnetic Measurements Digest Pub Date : 1994-06-27 DOI:10.1109/CPEM.1994.333434

C. Hamilton, C. Burroughs

引用次数: 12

Abstract

This paper reviews eight years of fabrication of 10-V Josephson array chips at NIST and the performance and reliability of these chips at 22 different standards laboratories. Failure mechanisms and statistical data on failure rates are presented for devices made with both Nb/Nb/sub 2/O/sub 5//Pb and Nb/Al/sub 2/O/sub 3//Nb junctions.<>

查看原文本刊更多论文

NIST 10-V约瑟夫森阵列的性能和可靠性

本文回顾了美国国家标准技术研究院(NIST) 8年来10-V约瑟夫森阵列芯片的制造过程，以及这些芯片在22个不同标准实验室的性能和可靠性。给出了Nb/Nb/sub 2/O/sub 5//Pb和Nb/Al/sub 2/O/sub 3//Nb结的失效机理和故障率的统计数据

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊