Designing QCA Delay-Insensitive Serial Adder

Abstract

Although QCA (quantum dot cellular automata) has been introduced as a new kind of technology for over a decade, it still continues to be so and its merits and flaws are yet under study for future practical use. One of the problems of this technology is the dependency of its circuit timing to its layout. An asynchronous design methodology for QCA has been offered to solve this problem. The proposed methodology uses NCL (null convention logic) to approach this issue. Since asynchronous registers play an important role in NCL methodology, to ease the problem this work is aimed to design asynchronous registers and employ them to construct a delay insensitive serial adder. The results obtained so far can be used to assess the required cell counts, and space in future QCA system design.