D. Kiran, B. Radheshyam, S. Gurunarayanan, J. P. Misra
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引用次数: 7
Abstract
In this paper, we propose a dynamic and efficient compiler based scheduling algorithm for multicore processors.Here, scheduler takes sub-blocks of a basic block which can be executed independently and maps these sub-blocks on to multiple cores to achieve less execution time. Instructions inside the sub-blocks are in Static-Single Assignment (SSA) form and have only true dependency, but all sub-blocks are disjoint. Scheduler is dynamic because, before mapping subblocks on to cores it checks the register requirement and cycles required for execution of each block and merges the sub-blocks if required which will lead to many outshoots. Despite having a number of new features, this algorithm has admissible time complexity, is economical in terms of the number of core used and is suitable for a wide range of graph structures.