A Sense-Amplifier Based Flip-Flop with Symmetric Latch Design

Abstract

Sense-amplifier based flip-flop circuit has been introduced with low power and high-speed characteristics. The design has a small clock load, simple structure, near-zero setup time and uses a lesser number of transistors. Also, the design has shown an improvement in performance and overall PDP when compared with flip-flop structures proposed previously for similar input/output conditions. The power consumption and delay in the circuit observed is of 2.41 µW and 34.94 ps respectively. The overall power-delay product has been improved. All the designs are proposed using Cadence Virtuoso Designing tools with CMOS 90nm technology.