A FinFET LER VT variability estimation scheme with 300× efficiency improvement

Abstract

In this paper, we have proposed a computationally efficient method to evaluate threshold voltage (VT) variability due to Line Edge Roughness (LER) in sub-20nm node FinFETs. For channel lengths less than 15 nm, the variability in threshold voltage may be estimated to a great accuracy (error <; 10%) with a decrease in computation time of over 300×. The method thus proposed provides a fast and accurate way of estimating σVT from LER specifications of a fin patterning technology.