FPGA-based scalable and highly concurrent convolutional neural network acceleration

Abstract

This article proposes an efficient, low-latency, scalable, and low-error neural network acceleration architecture. Considering the performance requirements of high efficiency and low latency, the methods of multi-channel parallel computing between layers and pipeline design are adopted to accelerate the neural network. Then, based on Xilinx zynq-7000 FPGA, the acceleration strategy is realized, and the effect of calculating 28*28 handwritten images at 25.95us at a clock frequency of 200M is investigated. Further, the flexibility and scalability of the network is improved by adding a line buffer for variable image width and designing a mechanism for selectable convolution kernel size. Since the convolutional neural networks are based on floating-point operations, if the floating-point is converted to fixed-point when implemented on FPGA, there will not only be a loss of precision, but also introduce a tedious conversion work. Thus, our neural network uses 32-bit Floating point operations. Moreover, the task of handwritten digit recognition is performed on the MNIST data set, to experimentally evaluate our solution. Experiment results show that the neural network acceleration architecture proposed in this paper achieves better performance. Compare with the literature [4],[6], the calculation speed is significantly improved, and the calculation speed is increased by 101.6 times compared with the literature [4] Compared with the literature [6], there is a speed increase of 11.88 times.