E. Micler, Ching-Te Li, A. Krishnan, C. Jin, M. Jain
{"title":"A charge damage study using an electron beam low k treatment","authors":"E. Micler, Ching-Te Li, A. Krishnan, C. Jin, M. Jain","doi":"10.1109/IITC.2004.1345740","DOIUrl":null,"url":null,"abstract":"Organosilicate glass (OSG) deposited by plasma enhanced chemical vapour deposition (PECVD) is a likely candidate for 65nm node low k interconnect dielectric. Electron beam (e-beam) treatment efficiently stiffens porous PECVD OSG and may enable extension of PECVD OSG beyond the 65 nm node. Charge damage during e-beam exposure should be considered before implementing e-beam treatments for low k dielectrics. The effects of e-beam cathode potential on CMOS transistor threshold voltage and gate dielectric leakage current are investigated using 130nm node CMOS transistors. The impact of e-beam treatments was negligible on devices with 1.7nm gate dielectrics, but can adversely impact the 6.7nm dielectric devices.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2004.1345740","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Organosilicate glass (OSG) deposited by plasma enhanced chemical vapour deposition (PECVD) is a likely candidate for 65nm node low k interconnect dielectric. Electron beam (e-beam) treatment efficiently stiffens porous PECVD OSG and may enable extension of PECVD OSG beyond the 65 nm node. Charge damage during e-beam exposure should be considered before implementing e-beam treatments for low k dielectrics. The effects of e-beam cathode potential on CMOS transistor threshold voltage and gate dielectric leakage current are investigated using 130nm node CMOS transistors. The impact of e-beam treatments was negligible on devices with 1.7nm gate dielectrics, but can adversely impact the 6.7nm dielectric devices.