Impact of Version Management for Transactional Memories on Phase-Change Memories

Felipe L. Teixeira, M. Pilla, A. R. D. Bois, D. Mossé
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Abstract

Two of the major issues in current computer systems are energy consumption and how to explore concurrent systems in a correct and efficient way. Solutions for these hazards may be sought both in hardware and in software. Phase-Change Memory (PCM) is a memory technology intended to replace DRAMs (Dynamic Random Access Memories) as the main memory, providing reduced static power consumption. Their main problem is related to write operations that are slow and wear their material. Transactional Memories are synchronization methods developed to reduce the limitations of lock-based synchronization. Their main advantages are related to being high-level and allowing composition and reuse of code, besides the absence of deadlocks. The objective of this study is to analyze the impact of different versioning managers (VMs) for transactional memories in PCMs. The lazy versioning/lazy acquisition scheme for version management presented the lowest wear on the PCM in 3 of 7 benchmarks analyzed, and results similar to the alternative versioning for the other 4~benchmarks. These results are related to the number of aborts of VMs, where this VM presents a much smaller number of aborts than the others, up to 39 times less aborts in the experiment with the benchmark Kmeans with 64 threads.
事务性记忆体版本管理对相变记忆体的影响
当前计算机系统的两个主要问题是能耗和如何以正确有效的方式探索并发系统。这些危险的解决方案可以在硬件和软件中寻找。相变存储器(PCM)是一种存储器技术,旨在取代dram(动态随机存取存储器)作为主存储器,提供更低的静态功耗。它们的主要问题与写操作缓慢和磨损材料有关。事务性内存是为减少基于锁的同步限制而开发的同步方法。它们的主要优点除了没有死锁外,还与高级和允许代码组合和重用有关。本研究的目的是分析不同版本管理器(vm)对pcm中事务性内存的影响。在分析的7个基准测试中,用于版本管理的延迟版本控制/延迟获取方案在3个基准测试中对PCM的损耗最小,其结果与其他4个基准测试的替代版本控制相似。这些结果与VM的中止次数有关,其中这个VM的中止次数比其他VM少得多,在使用64线程的基准Kmeans进行的实验中,中止次数减少了39倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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