A proposed low power voltage multiplier for passive UHF RFID transponder

Abstract

The design of a low power voltage multiplier for passive UHF RFID transponder which compatible with CMOS process and can be applied to the surroundings in where the distance from the reader changes greatly is presented in this paper. The functioning principle of N-stage voltage multiplier is introduced in this paper. With the intention of maximizing the operating range of RFID tag, low power design techniques are necessary. Therefore, the key design parameters optimization is discussed. The transistor size (W/L) and number of stages (N) are varied in order to attain the great value of output voltage and power efficiency. This proposed design is implemented in 0.18µm process. The calculated and simulated result shows that the four-stage voltage multiplier can work at frequency 900MHz by using 8µm transistor size and the power efficiency is 34% with output voltage 1.2V.